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CAT28F102
1 Megabit CMOS Flash Memory FEATURES
s Fast Read Access Time: 45/55/70/90 ns s Low Power CMOS Dissipation:
Licensed Intel second source
s 64K x 16 Word Organization s Stop Timer for Program/Erase s On-Chip Address and Data Latches s JEDEC Standard Pinouts:
-Active: 30 mA max (CMOS/TTL levels) -Standby: 1 mA max (TTL levels) -Standby: 100 A max (CMOS levels)
s High Speed Programming:
-10 s per byte -1 Sec Typ Chip Program
-40-pin DIP -44-pin PLCC -40-pin TSOP
s 100,000 Program/Erase Cycles s 10 Year Data Retention s Electronic Signature
s 0.5 Seconds Typical Chip-Erase s 12.0V
5% Programming and Erase Voltage
s Commercial,Industrial and Automotive
Temperature Ranges
DESCRIPTION
The CAT28F102 is a high speed 64K x 16-bit electrically erasable and reprogrammable Flash memory ideally suited for applications requiring in-system or after-sale code updates. Electrical erasure of the full memory contents is achieved typically within 0.5 second. It is pin and Read timing compatible with standard EPROM and E2PROM devices. Programming and Erase are performed through an operation and verify algorithm. The instructions are input via the I/O bus, using a two write cycle scheme. Address and Data are latched to free the I/O bus and address bus during the write operation. The CAT28F102 is manufactured using Catalyst's advanced CMOS floating gate technology. It is designed to endure 100,000 program/erase cycles and has a data retention of 10 years. The device is available in JEDEC approved 40-pin DIP, 44-pin PLCC, or 40-pin TSOP packages.
I/O0-I/O15
BLOCK DIAGRAM
I/O BUFFERS ERASE VOLTAGE SWITCH
WE
COMMAND REGISTER
PROGRAM VOLTAGE SWITCH
CE, OE LOGIC
DATA LATCH
SENSE AMP
CE OE
ADDRESS LATCH
Y-GATING Y-DECODER 1,048,576-BIT MEMORY ARRAY
A0-A15
X-DECODER
VOLTAGE VERIFY SWITCH
28F101-1
(c) 1998 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
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Doc. No. 25038-0A 2/98 F-1
CAT28F102
PIN CONFIGURATION
PIN FUNCTIONS
Pin Name A0-A15 I/O0-I/O15
A15 A14
Type Input I/O Input Input Input
Function Address Inputs for memory addressing Data Input/Output Chip Enable Output Enable Write Enable Voltage Supply Ground Program/Erase Voltage Supply No Connect
PLCC Package (N)
I/O13 I/O14 I/O15 CE VPP NC VCC WE NC
CE OE WE
A13 A12 A11 A10 A9 VSS NC A8 A7 A6 A5
I/O12 I/O11 I/O10 I/O9 I/O8 VSS NC I/O7 I/O6 I/O5 I/O4
7 8 9 10 11 12 13 14 15 16
6 5 4 3 2 1 44 43 42 41 40
39 38 37 36 35 34 33 32 31 30
VCC VSS VPP NC
29 17 18 19 20 21 22 23 24 25 26 27 28
I/O3 I/O2 I/O1 I/O0 OE NC A0 A1 A2 A3 A4
TSOP Package (T14)
A9 A10 A11 A12 A13 A14 A15 NC WE VCC VPP CE I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 I/O8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VSS A8 A7 A6 A5 A4 A3 A2 A1 A0 OE I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 VSS
28F101-3
28F101-2
DIP Package (P)
VPP CE I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 I/O8 VSS I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 OE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC WE NC A15 A14 A13 A12 A11 A10 A9 VSS A8 A7 A6 A5 A4 A3 A2 A1 A0
Reverse TSOP Package (T14R)
A0 A1 A2 A3 A4 A5 A6 A7 A8 GND A9 A10 A11 A12 A13 A14 A15 NC WE VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 OE I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 GND I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 VPP CE
28F102 TSOP2
Doc. No. 25038-0A 2/98 F-1
2
CAT28F102
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................... -55C to +95C Storage Temperature ....................... -65C to +150C Voltage on Any Pin with Respect to Ground(1) ........... -0.6V to +VCC + 2.0V Voltage on Pin A9 with Respect to Ground(1) ................... -2.0V to +13.5V VPP with Respect to Ground during Program/Erase(1) .............. -0.6V to +14.0V VCC with Respect to Ground(1) ............ -2.0V to +7.0V Package Power Dissipation Capability (TA = 25C) .................................. 1.0 W Lead Soldering Temperature (10 secs) ............ 300C Output Short Circuit Current(2) ........................ 100 mA RELIABILITY CHARACTERISTICS Symbol NEND
(3)
*COMMENT
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
Parameter Endurance Data Retention ESD Susceptibility Latch-Up
Min. 100K 10 2000 100
Max.
Units Cycles/Byte Years Volts mA
Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17
TDR(3) VZAP(3) ILTH(3)(4)
CAPACITANCE TA = 25C, f = 1.0 MHz Limits Symbol CIN
(3)
Test Input Pin Capacitance Output Pin Capacitance VPP Supply Capacitance
Min
Max. 6 10 25
Units pF pF pF
Conditions VIN = 0V VOUT = 0V VPP = 0V
COUT(3) CVPP
(3)
Note: (1) The minimum DC input voltage is -0.5V. During transitions, inputs may undershoot to -2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) This parameter is tested initially and after a design or process change that affects the parameter. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from -1V to VCC +1V.
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Doc. No. 25038-0A 2/98 F-1
CAT28F102
D.C. OPERATING CHARACTERISTICS VCC = +5V 10%, unless otherwise specified Limits Symbol ILI ILO ISB1 ISB2 ICC1 ICC2(1) ICC3(1) ICC4(1) IPPS IPP1 IPP2(1) IPP3(1) IPP4(1) VIL VILC VOL VIH VIHC VOH1 VOH2 VID IID(1) VLO Parameter Input Leakage Current Output Leakage Current VCC Standby Current CMOS VCC Standby Current TTL VCC Active Read Current VCC Programming Current VCC Erase Current VCC Prog./Erase Verify Current VPP Standby Current VPP Read Current VPP Programming Current VPP Erase Current VPP Prog./Erase Verify Current Input Low Level TTL Input Low Level CMOS Output Low Level Input High Level TTL Input High Level CMOS Output High Level TTL Output High Level CMOS A9 Signature Voltage A9 Signature Current VCC Erase/Prog. Lockout Voltage 2.5 2 VCC*0.7 2.4 VCC-0.4 11.4 13.0 200 -0.5 -0.5 Min. Max. 1 1 100 1 50 30 30 30 10 100 50 30 5 0.8 0.8 0.45 VCC+0.5 VCC+0.5 Unit A A A mA mA mA mA mA A A mA mA mA V V V V V V V V A V IOH = -2.5mA, VCC = 4.5V IOH = -400A, VCC = 4.5V A9 = VID A9 = VID IOL = 5.8mA, VCC = 4.5V Test Conditions VIN = VCC or VSS VCC = 5.5V, OE = VIH VOUT = VCC or VSS, VCC = 5.5V, OE = VIH CE = VCC 0.5V, VCC = 5.5V CE = VIH, VCC = 5.5V VCC = 5.5V, CE = VIL, IOUT = 0mA, f = 6 MHz VCC = 5.5V, Programming in Progress VCC = 5.5V, Erasure in Progress VCC = 5.5V, Program or Erase Verify in Progress VPP = VPPL VPP = VPPH VPP = VPPH, Programming in Progress VPP = VPPH, Erasure in Progress VPP = VPPH, Program or Erase Verify in Progress
Supply Characteristics VCC VCC VPPL VPPH VCC Supply Voltage VCC Supply Voltage VPP During Read Operations VPP During Read/Erase/Program 4.5 4.75 0 11.4 5.5 5.25 6.5 12.6 V V V V 28F102-70, 90 28F102-55, -45
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CAT28F102
A.C. CHARACTERISTICS, Read Operation
VCC = +5V 10%, unless otherwise specified
JEDEC Symbol tAVAV tELQV tAVQV tGLQV tAXQX tGLQX tELQX tGHQZ tEHQZ(1)(2) tWHGL Standard Symbol tRC tCE tACC tOE tOH tOLZ(1)(6) tLZ(1)(6) tDF(1)(2) Parameter Read Cycle Time CE Access Time Address Access Time OE Access Time Output Hold from Address OE/CE Chan OE to Output in Low-Z CE to Output in Low-Z OE High to Output High-Z CE High to Output High-Z Write Recovery Time Before Read 6 0 0 0 15 15 6 28F102-45(7)
Vcc=5V+5%
28F102-55(7) 28F102-70 (7) 28F102- 90 (8)
Vcc=5V+5%
Min. 45
Max.
Min. Max. Min. 55 70 55 55 25 0 0 0 15 15 6 0 0 0
Max.
Min. 90
Max
Unit ns
45 45 20
70 70 28 0 0 0 18 25 6
90 90 35
ns ns ns ns ns ns
20 30
ns ns s
Figure 1. A.C. Testing Input/Output Waveform(3)(4)(5)
2.4 V INPUT PULSE LEVELS 0.45 V 0.8 V
5108 FHD F03
2.0 V REFERENCE POINTS
Figure 2. A.C. Testing Load Circuit (example)
1.3V 1N914
3.3K DEVICE UNDER TEST OUT CL = 100 pF CL INCLUDES JIG CAPACITANCE
5108 FHD F04
Figure 3. High Speed A.C. Testing Input/Output Waveform(3)(4)(5)
3V 2.4 V
INPUT PULSE LEVELS 2.0 V 1.5V 0.8 V REFERENCE POINTS
0.0 0.45 V
Figure 4. High Speed A.C. Testing Load Circuit (example)
1.3V 1N914
3.3K DEVICE UNDER TEST OUT CL = 100 pF 30
CL INCLUDES JIG CAPACITANCE Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) Output floating (High-Z) is defined as the state where the external data line is no longer driven by the output buffer. (3) Input Rise and Fall Times (10% to 90%) < 10 ns. (4) Input Pulse Levels = 0.45V and 2.4V. For high speed input pulse levels 0.0V and 3.0V. (5) Input and Output Timing Reference = 0.8V and 2.0V. For high speed input and output timing reference=1.5V. (6) Low-Z is defined as the state where the external data may be driven by the output buffer but may not be valid. (7) For Load and Reference Points see Figures 3 and 4 (8) For Load and Reference Points see Figures 1 and 2
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Doc. No. 25038-0A 2/98 F-1
CAT28F102
A.C. CHARACTERISTICS, Program/Erase Operation VCC = +5V 10%, unless otherwise specified.
JEDEC Symbol tAVAV tAVWL tWLAX tDVWH tWHDX tELWL tWHEH tWLWH tWHWL tWHWH1(2) tWHWH2(2) tWHGL tGHWL tVPEL Standard Symbol tWC tAS tAH tDS tDH tCS tCH tWP tWPH Parameter Write Cycle Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time CE Setup Time CE Hold Time WE Pulse Width WE High Pulse Width Program Pulse Width Erase Pulse Width Write Recovery Time Before Read Read Recovery Time Before Write VPP Setup Time to CE 28F102-45 Min. Max. 45 0 30 30 10 0 0 30 20 10 9.5 6 0 100 28F102-55 Min. 55 0 30 30 10 0 0 30 20 10 9.5 6 0 100 Max. 28F102-70 28F102-90 Min. Max. Min. 70 0 35 35 10 0 0 35 20 10 9.5 6 0 100 90 0 40 40 10 0 0 40 20 10 9.5 6 0 100 Max. Unit ns ns ns ns ns ns ns ns ns s ms s s ns
VCC = +5V 5% VCC = +5V 5%
Erase and Programming Performance (1) 28F102-45 Parameter
Chip Erase Time (3)(5) Chip Program Time(3)(4)
28F102-55
28F102-70
28F102-90
Max. 10 6.5 Unit sec sec
Min. Typ. Max. Min. Typ. Max. Min. Typ. 0.5 1 10 6.5 0.5 1 10 6.5 0.5 1
Max. Min. Typ. 10 6.5 0.5 1
Note: (1) Please refer to Supply characteristics for the value of VPPH and VPPL. The VPP supply can be either hardwired or switched. If VPP is switched, VPPL can be ground, less than VCC + 2.0V or a no connect with a resistor tied to ground. (2) Program and Erase operations are controlled by internal stop timers. (3) `Typicals' are not guaranteed, but based on characterization data. Data taken at 25C, 12.0V VPP. (4) Minimum byte programming time (excluding system overhead) is 16 s (10 s program + 6 s write recovery), while maximum is 400 s/ byte (16 s x 25 loops). Max chip programming time is specified lower than the worst case allowed by the programming algorithm since most bytes program significantly faster than the worst case byte. (5) Excludes 00H Programming prior to Erasure.
Doc. No. 25038-0A 2/98 F-1
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CAT28F102
FUNCTION TABLE(1) Pins Mode Read Output Disable Standby Signature (MFG) Signature (Device) Program/Erase Write Cycle Read Cycle Output Disable Standby CE VIL VIL VIH VIL VIL VIL VIL VIL VIL VIH OE VIL VIH X VIL VIL VIH VIH VIL VIH X WE VIH VIH X VIH VIH VIL VIL VIH VIH X VPP VPPL X VPPL VPPL X VPPH VPPH VPPH VPPH VPPH I/O DOUT High-Z High-Z 0031H 0051H DIN DIN DOUT High-Z High-Z A0 = VIL, A9 = 12V A0 = VIH, A9 = 12V See Command Table During Write Cycle During Write Cycle During Write Cycle During Write Cycle Notes
WRITE COMMAND TABLE Commands are written into the command register in one or two write cycles. The command register can be altered only when VPP is high and the instruction byte is latched on the rising edge of WE. Write cycles also internally latch addresses and data required for programming and erase operations. Pins First Bus Cycle Mode Set Read Read Sig. (MFG) Read Sig. (Device) Erase Erase Verify Program Program Verify Reset Operation Write Write Write Write Write Write Write Write Address X X X X AIN X X X DIN XX00H XX90H XX90H XX20H XXA0H XX40H XXC0H XXFFH Operation Read Read Read Write Read Write Read Write Second Bus Cycle Address AIN 0000 0001 X X AIN X X XXFFH DIN DOUT XX20H DOUT DIN DOUT DOUT 0031H 0051H
Note: (1) Logic Levels: X = Logic `Do not care' (VIH, VIL, VPPL, VPPH)
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CAT28F102
READ OPERATIONS
Read Mode A Read operation is performed with both CE and OE low and with WE high. VPP can be either high or low, however, if VPP is high, the Set READ command has to be sent before reading data (see Write Operations). The data retrieved from the I/O pins reflects the contents of the memory location corresponding to the state of the 16 address pins. The respective timing waveforms for the read operation are shown in Figure 5. Refer to the AC Read characteristics for specific timing parameters. Signature Mode The signature mode allows the user to identify the IC manufacturer and the type of device while the device resides in the target system. This mode can be activated in either of two ways; through the conventional method of applying a high voltage (12V) to address pin A9 or by sending an instruction to the command register (see Write Operations). The conventional mode is entered as a regular READ mode by driving the CE and OE pins low (with WE high), and applying the required high voltage on address pin A9 while all other address lines are held at VIL. A Read cycle from address 0000H retrieves the binary code for the IC manufacturer on outputs I/O0 to I/O15: CATALYST Code = 0000 0000 0011 0001 (0031H) A Read cycle from address 0001H retrieves the binary code for the device on outputs I/O0 to I/O15. 28F102 Code = 0000 0000 0101 0001 (0051H) Standby Mode With CE at a logic-high level, the CAT28F102 is placed in a standby mode where most of the device circuitry is disabled, thereby substantially reducing power consumption. The outputs are placed in a high-impedance state.
Figure 5. A.C. Timing for Read Operation
POWER UP
STANDBY
DEVICE AND ADDRESS SELECTION
OUPUTS ENABLED
DATA VALID
STANDBY
POWER DOWN
ADDRESSES
ADDRESS STABLE tAVAV (tRC)
CE (E)
tEHQZ(tDF)
OE (G)
tWHGL tGHQZ (tDF) tGLQV (tOE) tELQV (tCE) tGLQX (tOLZ) tELQX (tLZ) tAXQX(tOH)
WE (W)
HIGH-Z DATA (I/O)
tAVQV (tACC) OUTPUT VALID
HIGH-Z
28F102 F05
28F102 Fig. 6
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CAT28F102
WRITE OPERATIONS
The following operations are initiated by observing the sequence specified in the Write Command Table. Read Mode The device can be put into a standard READ mode by initiating a write cycle with XX00H on the data bus. The subsequent read cycles will be performed similar to a standard EPROM or E2PROM Read. Signature Mode An alternative method for reading device signature (see Read Operations Signature Mode), is initiated by writing the code XX90H into the command register while keeping VPP high. A read cycle from address 0000H with CE and OE low (and WE high) will output the device signature. CATALYST Code = 0000 0000 0011 0001 (0031H)
A Read cycle from address 0001H retrieves the binary code for the device on outputs I/O0 to I/O7. 28F102 Code = 0000 0000 0101 0001 (0051H) Erase Mode During the first Write cycle, the command XX20H is written into the command register. In order to commence the erase operation, the identical command of XX20H has to be written again into the register. This two-step process ensures against accidental erasure of the memory contents. The final erase cycle will be stopped at the rising edge of WE, at which time the Erase Verify command (XXA0H) is sent to the command register. During this cycle, the address to be verified is sent to the address bus and latched when WE goes low. An integrated stop timer allows for automatic timing control over this operation, eliminating the need for a maximum erase timing specification. Refer to AC Characteristics (Program/Erase) for specific timing parameters.
Figure 6. A.C. Timing for Erase Operation
VCC POWER-UP & STANDBY SETUP ERASE COMMAND ERASE COMMAND ERASING ERASE VERIFY COMMAND ERASE VCC POWER-DOWN/ VERIFICATION STANDBY
ADDRESSES tWC tWC tAS CE (E) tCS tCH OE (G) tGHWL tWPH WE (W) tWP tDS HIGH-Z DATA (I/O) DATA IN = XX20H tDH tDS tWP tDH tWP tDS tDH DATA IN = XXA0H tLZ tCE VCC 5.0V 0V VPP VPPH VPPL tVPEL VALID DATA OUT tOE tOLZ tOH tWHWH2 tWHGL tDF tCH tCS tCH tEHQZ tWC tAH tRC
DATA IN = XX20H
28F102 Fig. 6
28F102 F06
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Doc. No. 25038-0A 2/98 F-1
CAT28F102
Figure 7. Chip Erase Algorithm(1)
START ERASURE BUS OPERATION COMMAND COMMENTS
APPLY VPPH
VPP RAMPS TO VPPH (OR VPP HARDWIRED) ALL BYTES SHALL BE PROGRAMMED TO 00 BEFORE AN ERASE OPERATION INITIALIZE ADDRESS
PROGRAM ALL BYTES TO 0000H
STANDBY
INITIALIZE ADDRESS
INITIALIZE PLSCNT = 0
PLSCNT = PULSE COUNT
WRITE ERASE SETUP COMMAND
DATA = XX20H WRITE ERASE
WRITE ERASE COMMAND
WRITE
ERASE
DATA = XX20H
TIME OUT 10ms
WAIT
WRITE ERASE VERIFY COMMAND
WRITE
ERASE VERIFY
ADDRESS = BYTE TO VERIFY DATA = XXA0H STOPS ERASE OPERATION
TIME OUT 6s INCREMENT ADDRESS READ DATA FROM DEVICE NO DATA = FFH? YES NO LAST ADDRESS? YES WRITE READ COMMAND WRITE READ NO INC PLSCNT = 1000 ? YES STANDBY READ
WAIT
READ BYTE TO VERIFY ERASURE
COMPARE OUTPUT TO FF INCREMENT PULSE COUNT
DATA = 0000H RESETS THE REGISTER FOR READ OPERATION VPP RAMPS TO VPPL (OR VPP HARDWIRED)
APPLY VPPL
APPLY VPPL
STANDBY
ERASURE COMPLETED
ERASE ERROR
28F101-07
Note: (1) The algorithm MUST BE FOLLOWED to ensure proper and reliable operation of the device.
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CAT28F102
Erase-Verify Mode The Erase-verify operation is performed on every byte after each erase pulse to verify that the bits have been erased. Programming Mode The programming operation is initiated using the programming algorithm of Figure 9. During the first write cycle, the command XX40H is written into the command register. During the second write cycle, the address of the memory location to be programmed is latched on the falling edge of WE, while the data is latched on the rising edge of WE. The program operation terminates with the next rising edge of WE. An integrated stop timer allows for automatic timing control over this operation, eliminating the need for a maximum program timing specification. Refer to AC Characteristics (Program/Erase) for specific timing parameters. Program-Verify Mode A Program-verify cycle is performed to ensure that all bits have been correctly programmed following each byte programming operation. The specific address is already latched from the write cycle just completed, and stays latched until the verify is completed. The Programverify operation is initiated by writing XXC0H into the command register. An internal reference generates the necessary high voltages so that the user does not need to modify VCC. Refer to AC Characteristics (Program/ Erase) for specific timing parameters.
Figure 8. A.C. Timing for Programming Operation
PROGRAM VCC POWER-UP SETUP PROGRAM LATCH ADDRESS COMMAND & DATA VERIFY & STANDBY PROGRAMMING COMMAND PROGRAM VCC POWER-DOWN/ VERIFICATION STANDBY
ADDRESSES tWC tAS CE (E) tCS tCH OE (G) tGHWL tWPH WE (W) tWP tDS HIGH-Z DATA (I/O) DATA IN = XX 40H tDH tDS tWP tDH tWP tDS tDH DATA IN = XX C0H tLZ tCE VCC 5.0V 0V VPP VPPH VPPL
28F102 F07
tWC tAH
tRC
tCH tCS
tCH
tEHQZ
tWHWH1
tWHGL
tDF
tOE tOLZ
tOH
DATA IN
VALID DATA OUT
tVPEL
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CAT28F102
Figure 9. Programming Algorithm(1)
START PROGRAMMING BUS OPERATION
COMMAND
COMMENTS
APPLY VPPH
STANDBY
VPP RAMPS TO VPPH (OR VPP HARDWIRED)
INITIALIZE ADDRESS
INITIALIZE ADDRESS
PLSCNT = 0
INITIALIZE PULSE COUNT PLSCNT = PULSE COUNT
WRITE SETUP PROG. COMMAND
1ST WRITE CYCLE
WRITE SETUP
DATA = XX40H
WRITE PROG. CMD ADDR AND DATA
2ND WRITE CYCLE
PROGRAM
VALID ADDRESS AND DATA
TIME OUT 10s
WAIT
WRITE PROGRAM VERIFY COMMAND
1ST WRITE CYCLE
PROGRAM VERIFY
DATA = XXC0H
TIME OUT 6s
WAIT
READ DATA FROM DEVICE NO VERIFY DATA ? YES INCREMENT ADDRESS NO LAST ADDRESS? YES WRITE READ COMMAND NO INC PLSCNT = 25 ? YES
READ
READ BYTE TO VERIFY PROGRAMMING
STANDBY
COMPARE DATA OUTPUT TO DATA EXPECTED
1ST WRITE CYCLE
READ
DATA = XX00H SETS THE REGISTER FOR READ OPERATION VPP RAMPS TO VPPL (OR VPP HARDWIRED)
APPLY VPPL
APPLY VPPL
STANDBY
PROGRAMMING COMPLETED
PROGRAM ERROR
Note: (1) The algorithm MUST BE FOLLOWED to ensure proper and reliable operation of the device.
28F101-09
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CAT28F102
Abort/Reset An Abort/Reset command is available to allow the user to safely abort an erase or program sequence. Two consecutive program cycles with XXFFH on the data bus will abort an erase or a program operation. The abort/reset operation can interrupt at any time in a program or erase operation and the device is reset to the Read Mode.
POWER UP/DOWN PROTECTION
The CAT28F102 offers protection against inadvertent programming during VPP and VCC power transitions. When powering up the device there is no power-on sequencing necessary. In other words, VPP and VCC may power up in any order. Additionally VPP may be hardwired to VPPH independent of the state of VCC and any power up/down cycling. The internal command register of the CAT28F102 is reset to the Read Mode on power up.
DATA PROTECTION
1. Power Supply Voltage When the power supply voltage (VCC) is less than 2.5V, the device ignores WE signal. 2. Write Inhibit When CE and OE are terminated to the low level, write mode is not set.
POWER SUPPLY DECOUPLING
To reduce the effect of transient power supply voltage spikes, it is good practice to use a 0.1F ceramic capacitor between VCC and VSS and VPP and VSS. These high-frequency capacitors should be placed as close as possible to the device for optimum decoupling.
Figure 10. Alternate A.C. Timing for Program Operation
PROGRAM VCC POWER-UP SETUP PROGRAM LATCH ADDRESS COMMAND & DATA VERIFY & STANDBY PROGRAMMING COMMAND PROGRAM VCC POWER-DOWN/ VERIFICATION STANDBY
ADDRESSES tWC tAVEL WE (E) tWLEL tEHWH OE (G) tGHEL CE (W) tEHDX DATA IN = XX40H tELEH tDVEH DATA IN tELEH tEHDX tDVEH DATA IN = XXC0H tLZ tCE VCC 5.0V 0V VPP VPPH VPPL
28F102 F10
tWC tELAX
tRC
tWLEL
tEHWH tWLEL
tEHWH
tEHQZ
tEHEH tEHEL
tEHGL
tDF
tDVEH HIGH-Z DATA (I/O)
tOE tEHDX tOLZ
tOH
VALID DATA OUT
tVPEL
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CAT28F102
ALTERNATE CE-CONTROLLED WRITES VCC = +5V 10%, unless otherwise specified.
28F102-45 JEDEC Symbol tAVAV tAVEL tELAX tDVEH tEHDX tEHGL tGHEL tWLEL tEHWH tELEH tEHEL tVPEL Standard Symbol
WC
28F102-55
VCC = +5V 5%
28F102-70 Min. 70 0 35 35 10 6 0 0 0 35 20 100 Max.
28F102-90 Min. 90 0 40 40 10 6 0 0 0 40 20 100 Max. Unit ns ns ns ns ns s s ns ns ns ns ns
VCC = +5V 5%
Parameter Write Cycle Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time Write Recovery Time Before Read Read Recovery Time Before Write WE Setup Time Before CE WE Hold Time After CE Write Pulse Width Write Pulse Width High VPP Setup Time to CE Low
Min. 45 0 30 30 10 6 0 0 0 30 20 100
Max.
Min. 55 0 30 30 10 6 0 0 0 30 20 100
Max.
tAS tAH tDS
tDH
tWS tWH tCP tCPH -
ORDERING INFORMATION
Prefix CAT Device # 28F102 N Suffix I -90 T
Product Number
Temperature Range Blank = Commercial (0 - 70C) I = Industrial (-40 - 85C) A = Automotive (-40 - 105C)* Package N: PLCC P: PDIP T14: TSOP T14R: TSOP
Tape & Reel T: 500/Reel
Optional Company ID
Speed 45: 45ns 55: 55ns 70: 70ns 90: 90ns
*-40o to + 125oC is available upon request Note: (1) The device used in the above example is a CAT28F102NI-90T (PLCC, Industrial Temperature, 90 ns access time, Tape & Reel).
Doc. No. 25038-0A 2/98 F-1
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Price & Availability of CAT28F102

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